1. Field of the Invention
This invention relates to a dynamic random access memory (DRAM) device and a semiconductor integrated circuit device, and more particularly to an improvement of the refresh operations.
2. Description of the Relates Background Art
For DRAMs, refreshment of memory cell data is indispensable, and it is necessary to refresh data of all memory cells within a predetermined length of time. If refreshment is not effected properly, reading of data will be disabled due to leakage of charges from memory cells.
The time required for refreshment is getting longer and longer as the DRAM capacity increases, and particular consideration has been required about influences of the longer time for refreshment to the performance of DRAM systems. More specifically, although refresh operation of typical DRAM is controlled by a memory controller, or the like, the time spent by the memory controller for issuance of refresh requests increase, and it oppresses the time for the ordinary operation.
As an solution of this problem, there is a method of refreshing a plurality of sub-arrays simultaneously with a single refresh command from the memory controller. With this method, refresh commands from the memory controller can be reduced, and the load to the memory controller can be alleviated. This is a technique that has been employed for years.
On the other hand, for the purpose of improving the performance of a large-capacity DRAM system, a xe2x80x9cmulti-bank systemxe2x80x9d has come to be employed recently. With this system, access time can be reduced substantially by calling interleave operation, which makes an access time and another partly overlap when a plurality of banks are accessed to.
In recent DRAMs, a xe2x80x9cshared sense-amplifier systemxe2x80x9d in which adjacent sub-arrays share a sense-amplifier in order to improve the efficiency per unit area. This system can reduce the area of the sense-amplifier circuit region close to xc2xd of those of systems other than the shared sense-amplifier system.
There has been also proposed a xe2x80x9cnon-independent bank systemxe2x80x9d simultaneously employing the xe2x80x9cmulti-bank systemxe2x80x9d and the xe2x80x9cshared sense-amplifier systemxe2x80x9d (See xe2x80x9cA 1.6 Gigabytes DRAM-with Flexible Mapping Redundancy Technique and Additional Refresh Schemexe2x80x9d, 1999 ISSC digest of technical papers, pp. 410 (ISSN 0193-6530). In this system, adjacent banks are not independent from each other, and share a common sense-amplifier circuit. Thus, advantages of both the multi-bank system and the shared sense-amplifier system can be retained altogether.
However, in case of the non-independent bank system, there is a constraint as a result of using the shared sense-amplifier system, and it is not possible to simultaneously activate two banks sharing a sense-amplifier circuit. Although a shared sense-amplifier circuit can be commonly used by two sub-arrays, while it is used by one of the sub-arrays, it has be disconnected from the other sub-array. This constraint on operation also applies to refresh operation. Also upon activation for refresh operation, in case of sub-arrays sharing a common sense amplifier circuit, unless one of them is set in a precharged state, the other cannot be activated.
The constraint on operation discussed above adversely affects the performance of the DRAM system. For example, when it is desired to start refresh operation of a particular sub-array, if an adjacent sub-array commonly sharing a sense amplifier circuit with the particular sub-array is currently activated, the system has to wait until the adjacent sub-array is set in the precharged state. Further, during ordinary operation, when data of a particular sub-array should be accessed to, in the case where the system is configured to preferentially effectuate refresh operation when a refresh request comes to the adjacent sub-array sharing the common sense amplifier circuit, it is necessary to one precharge the particular sub-array, wait that the adjacent sub-array completes its refresh operation and precharges, and thereafter active the particular sub-array.
It is therefore an object of the invention to provide a DRAM of a non-independent bank system which enables high-speed operation by reducing the occurrence probability of operation constraint and improves the system performance. It is also an object of the invention to provide a semiconductor integrated circuit device incorporating such DRAM and a logic circuit.
The present invention is characterized in a dynamic random access memory device having a plurality of banks each including a plurality of sub-arrays, and a sense amplifier circuit commonly shared by sub-arrays in different banks, which has a row access mode for activating a sub-array selected from each said bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each said bank at substantially the same timing to refresh the memory cell data therein, the number of sub-arrays in a single bank activated at substantially the same timing in said refresh mode being larger than the number of sub-arrays in a single bank activated in said row access mode. Activating a plurality of sub-arrays at substantially the same timing means activating a plurality of sub-arrays in response to a single command from a memory controller. Therefore, in response to a single command from the memory controller, the plurality of sub-arrays may be activated with a time difference inside the memory.
According to the invention, by activating a larger number of sub-arrays in a single bank at the same time in the refresh mode, the load to the memory controller can be alleviated, and this contributes to an improvement of the performance of the DRAM system. Further, by activating a larger number of sub-arrays in a single bank at substantially the same timing, the number of banks activated at substantially the same timing can be reduced, and this contributes to decreasing the occurrence of operation constraints peculiar to non-independent bank structures employing a shared sense-amplifier system. As a result, useless precharge period is no longer required, and a high effective data transfer rate and high operation are ensured.
More specifically, in the present invention, it is possible to design the device so that, within each bank, a plurality of sub-arrays do not commonly share a sense amplifier, and all sub-arrays in one bank are activated at substantially the same timing in the refresh mode. In this manner, operation constraints are minimized.
In the present invention, the device may be designed to provide a plurality of independent blocks each including a plurality of sub-arrays so that, in each block, a plurality of adjacent sub-arrays share a sense amplifier circuit, and a plurality of sub-arrays selected from each block constitute a single bank.
In this case, for a decoding circuit for selecting a single sub-array from a single bank in the row access mode in response to a bank address and a block designating address (for example, most significant bit of a row address), a refresh control circuit may be provided, which restricts the block selecting function in the refresh mode in response to the refresh signal to activate a plurality of sub-arrays in a single bank at substantially the same timing.
In the case where there is provided, in addition to the decoding circuit, a page length variable signal line for restricting the block selecting function of the decoding circuit and activating a plurality of sub-arrays in a single bank at the same time, the page length variable signal line can be used as a refresh control line for restricting the block selecting function of the decoding circuit in the refresh mode and activating a plurality of sub-arrays in a single bank at substantially the same timing.
Furthermore, in the present invention, in the case where a plurality of sub-arrays are arranged to share a sense amplifier circuit between adjacent ones, addresses can be set so that every other sub-arrays are designated as one bank in the order of arrangement, and one end of the arrangement is the least significant bank address while the other end of the arrangement is the most significant bank address.